Book/Dissertation / PhD Thesis FZJ-2017-07235

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png
Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications



2017
Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag Jülich
ISBN: 978-3-95806-259-7

Jülich : Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag, Schriften des Forschungszentrums Jülich. Reihe Schlüsseltechnologien / Key Technologies 154, II, 136 S. () = RWTH Aachen, Diss., 2017

Please use a persistent id in citations:  

Abstract: In the era of portable electronic devices energy efficient integrated circuits (ICs) are highly demanded where the power consumption needs to be minimized by the reduction of the supply voltage V$_{dd}$. Digitl ciruits based on the contemplementary metal-oxide-semiconductor field effect transistors (MOSFETs), however, owns a physical limit of the minimum inverse sub-threshold slope (SS) of 60 mV/dec at room temperature. As consequence, the reduction of V$_{dd}$ either leads to low ON-current or inceases the OFF-current exponentally which in turn results in high power device concept with the potential to replace MOSFETs in low power applications. In comparson, TFETs can offer steeper transition between of OFF and the ON-state (SS<60mV/dec) since the current transport mechamism relies on band-to-band tunneling. Within the framework of this thesis strained Si gate-all-around (GAA) nanowire TFETs are ddddddddddfabricated in order to achieve high tunneling currents and small SS. Very small namowires, down to 5 mm in thickness and down to 15 nm in width, are surrounded by HfO$_{2}$/TiN as high-$\textit{k}$ dielectric and metal gate to obtain optimal gate electrostatics for the device. Tilted ion i mplantation into the performed thin epitaxial NiSi$_{2}$ has been performed to benefit from dopant segregation that results in sharper doping profile for source and drain. Strained Si GAA nanowire p- and n-TFETs have been characterized indicating comparable current performance with 5 $\mu$A/$\mu$m at V$_{dd}$=0.5 V. SS below 69 mV/dec has been measured for the n-TFET for I$_{d}$ < 10$^{-4} \mu$m at V$_{ds}$ = 0.1 V at room temperature. However, most of the switching characteristics of the TFETs yield SS larger than the thermal limit. Trap-assisted tunneling is found to be the main root cause. [...]


Note: RWTH Aachen, Diss., 2017

Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (PGI-9)
Research Program(s):
  1. 899 - ohne Topic (POF3-899) (POF3-899)

Appears in the scientific report 2017
Database coverage:
Creative Commons Attribution CC BY 4.0 ; OpenAccess
Click to display QR Code for this record

The record appears in these collections:
Document types > Theses > Ph.D. Theses
Institute Collections > PGI > PGI-9
Document types > Books > Books
Workflow collections > Public records
Publications database
Open Access

 Record created 2017-10-27, last modified 2022-09-30