- AutorIn
- Gerhard P. Fettweis
- Najeeb ul Hassan
- Lukas Landau
- Erik Fischer
- Titel
- Wireless Interconnect for Board and Chip Level
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa-118302
- Quellenangabe
- Proceedings of the Design Automation and Test in Europe (DATE), 2013, S. 958 - 963, ISSN: 1530-1591
- Erstveröffentlichung
- 2013
- ISBN
- 978-3-9815370-0-0
- Abstract (EN)
- Electronic systems of the future require a very high bandwidth communications infrastructure within the system. This way the massive amount of compute power which will be available can be inter-connected to realize future powerful advanced electronic systems. Today, electronic inter-connects between 3D chip-stacks, as well as intra-connects within 3D chip-stacks are approaching data rates of 100 Gbit/s soon. Hence, the question to be answered is how to efficiently design the communications infrastructure which will be within electronic systems. Within this paper approaches and results for building this infrastructure for future electronics are addressed.
- Andere Ausgabe
- DOI: 10.7873/DATE.2013.201
- Metadaten und Abstract des Artikels, der zuerst im Konferenzband Proceedings of the Design Automation and Test in Europe bei IEEE erschienen ist.
Link: http://dx.doi.org/10.7873/DATE.2013.201 - Freie Schlagwörter (DE)
- Elektronische Systeme, Kommunikationsinfrastruktur, Sonderforschungsbereich 912, Hochadaptive Energieeffiziente Systeme
- Freie Schlagwörter (EN)
- Electronic systems, communications infrastructure, Collaborative Research Centre 912, Highly Adaptive Energy-Efficient Computing
- Klassifikation (DDC)
- 620, 621.3
- Klassifikation (RVK)
- ZN 6420
- Publizierende Institution
- Technische Universität Dresden, Dresden
- URN Qucosa
- urn:nbn:de:bsz:14-qucosa-118302
- Veröffentlichungsdatum Qucosa
- 11.07.2013
- Dokumenttyp
- Konferenzbeitrag
- Sprache des Dokumentes
- Englisch
- Lizenz / Rechtehinweis