- AutorIn
- Paul Richard Genßler
- Titel
- Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa-191286
- Übersetzter Titel (DE)
- Virtualisierung von FPGA-Ressourcen mittels partieller dynamischer Rekonfiguration für konkurrierende Nutzerdesigns
- Datum der Einreichung
- 30.10.2015
- Datum der Verteidigung
- 12.03.2015
- Abstract (EN)
- Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.
- Freie Schlagwörter (DE)
- FPGA, Cloud, RC2F, RC3E, ICAP, XILINX, Rekonfiguration, Partielle
- Freie Schlagwörter (EN)
- FPGA, Cloud, RC2F, RC3E, ICAP, XILINX, Reconfiguration, Partial, Multiuser
- Klassifikation (DDC)
- 004
- Klassifikation (RVK)
- ST 260
- Normschlagwörter (GND)
- FPGA, Cloud, RC2F, RC3E, ICAP, XILINX, Reconfiguration, Partial
- BetreuerIn
- Prof. Dr.-Ing. habil. Rainer G. Spallek
- Dipl.-Inf. Oliver Knodel
- Den akademischen Grad verleihende / prüfende Institution
- Technische Universität Dresden, Dresden
- URN Qucosa
- urn:nbn:de:bsz:14-qucosa-191286
- Veröffentlichungsdatum Qucosa
- 07.01.2016
- Dokumenttyp
- Studienarbeit
- Sprache des Dokumentes
- Englisch
- Lizenz / Rechtehinweis