@unpublished{Kuchem1996Wirin-6131,
  year={1996},
  title={Wiring Edge-Disjoint Layouts},
  author={Kuchem, Ruth and Wagner, Dorothea}
}

<rdf:RDF
    xmlns:dcterms="http://purl.org/dc/terms/"
    xmlns:dc="http://purl.org/dc/elements/1.1/"
    xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
    xmlns:bibo="http://purl.org/ontology/bibo/"
    xmlns:dspace="http://digital-repositories.org/ontologies/dspace/0.1.0#"
    xmlns:foaf="http://xmlns.com/foaf/0.1/"
    xmlns:void="http://rdfs.org/ns/void#"
    xmlns:xsd="http://www.w3.org/2001/XMLSchema#" > 
  <rdf:Description rdf:about="https://kops.uni-konstanz.de/server/rdf/resource/123456789/6131">
    <dc:contributor>Kuchem, Ruth</dc:contributor>
    <bibo:uri rdf:resource="http://kops.uni-konstanz.de/handle/123456789/6131"/>
    <dcterms:hasPart rdf:resource="https://kops.uni-konstanz.de/bitstream/123456789/6131/1/preprint_010.pdf"/>
    <dc:date rdf:datatype="http://www.w3.org/2001/XMLSchema#dateTime">2011-03-24T16:09:43Z</dc:date>
    <dcterms:issued>1996</dcterms:issued>
    <dc:language>eng</dc:language>
    <foaf:homepage rdf:resource="http://localhost:8080/"/>
    <dcterms:isPartOf rdf:resource="https://kops.uni-konstanz.de/server/rdf/resource/123456789/36"/>
    <dc:contributor>Wagner, Dorothea</dc:contributor>
    <dc:creator>Wagner, Dorothea</dc:creator>
    <void:sparqlEndpoint rdf:resource="http://localhost/fuseki/dspace/sparql"/>
    <dc:creator>Kuchem, Ruth</dc:creator>
    <dc:rights>terms-of-use</dc:rights>
    <dcterms:available rdf:datatype="http://www.w3.org/2001/XMLSchema#dateTime">2011-03-24T16:09:43Z</dcterms:available>
    <dspace:isPartOfCollection rdf:resource="https://kops.uni-konstanz.de/server/rdf/resource/123456789/36"/>
    <dcterms:abstract xml:lang="eng">We consider the  wiring  or  layer assignment problem  for edge-disjoint layouts. The wiring problem is well understood for the case that the underlying layout graph is a square grid. Nothing is known so far for wiring edge-disjoint layouts in arbitrary planar layout graphs respectively layouts in the plane. In this paper, we introduce a general approach to this problem. We give equivalent conditions for k-layer wirability of edge-disjoint layouts in the plane. Based on these conditions, we obtain linear-time algorithms to wire every layout in a tri-hexagonal grid, respectively every layout in a tri-square-hexagonal grid using at most five layers.</dcterms:abstract>
    <dc:format>application/pdf</dc:format>
    <dcterms:rights rdf:resource="https://rightsstatements.org/page/InC/1.0/"/>
    <dspace:hasBitstream rdf:resource="https://kops.uni-konstanz.de/bitstream/123456789/6131/1/preprint_010.pdf"/>
    <dcterms:title>Wiring Edge-Disjoint Layouts</dcterms:title>
  </rdf:Description>
</rdf:RDF>