Fault tolerant routing algorithm for fully- and partially-defective NoC switches

Abstract

Recently network-on-chip (NoC) has become a broad topic of research and development and is going to displace bus and crossbar approaches for Systems-on-chip interconnection. NoCs provide the needs of an efficient communication infrastructure of complex SoC. In order to meet the communication requirements even in presence of faults, fault tolerant routing algorithms become one of the most dominant issues for NoC systems. There has been significant works on fault tolerant routing algorithms for NoCs which mostly support only fully defective switches, but in this thesis, a new deadlock and live-lock free fault tolerant routing algorithm that tolerates fully- and partially-defective NoC switches will be introduced. The proposed algorithm is an enhancement of the available region-based approach for NoCs. The novelty of our approach is that link failures are modeled as semi-faulty switches and as a result the faulty region is smaller and less healthy switches are deactivated. The algorithm does not need any virtual channel. In addition, the routing algorithm does not require routing table in every switch. The performance comparison shows the advantages of the proposed algorithm with state-of-the-art fault tolerant routing algorithms. Since our algorithm has less deactivated switches it has always higher throughput and less latency.