Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario; Kalte, Heiko; Rückert, Ulrich

Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

Langen D, Niemann J-C, Porrmann M, Kalte H, Rückert U (2002)
In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany.

Konferenzbeitrag | Veröffentlicht | Englisch

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Implementation_of_a_RISC_Processor_Core_for_SoC_Designs_-_FPGA_Prototype_vs._ASIC_Implementation.pdf

URN

urn:nbn:de:0070-pub-22885658

Autor*in

Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario^UniBi ; Kalte, Heiko; Rückert, Ulrich^UniBi

Einrichtung

Technische Fakultät > AG Kognitronik und Sensorik

Abstract / Bemerkung

In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding special, optimized hardware blocks for various operations. The effects on area and power consumption as well as computational power are analyzed. A detailed overview of the implementation of additional hardware multipliers and their effects on the above mentioned topics concludes this paper.

Erscheinungsjahr

2002

Titel des Konferenzbandes

Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC)

Page URI

https://pub.uni-bielefeld.de/record/2288565

Zitieren

Langen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.

Langen, D., Niemann, J. - C., Porrmann, M., Kalte, H., & Rückert, U. (2002). Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC) Hamburg, Germany.

Langen, Dominik, Niemann, Jörg-Christian, Porrmann, Mario, Kalte, Heiko, and Rückert, Ulrich. 2002. “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation”. In Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany.

Langen, D., Niemann, J. - C., Porrmann, M., Kalte, H., and Rückert, U. (2002). “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation” in Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC) (Hamburg, Germany).

Langen, D., et al., 2002. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany.

D. Langen, et al., “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation”, Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany: 2002.

Langen, D., Niemann, J.-C., Porrmann, M., Kalte, H., Rückert, U.: Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany (2002).

Langen, Dominik, Niemann, Jörg-Christian, Porrmann, Mario, Kalte, Heiko, and Rückert, Ulrich. “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation”. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany, 2002.

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